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See:
Description
| Class Summary | |
| BuildWrapper | Includes functionality for loading a design directly into cvt. |
| Edi2JHDL | Generates a JHDL circuit for the designated EdifCellInstance. |
| EdifBlackBoxCell | Represents a Black box for the new JHDL circuit being built. |
| JHDLWrapper | Builds a JHDL Wrapper circuit from an Edif file with a passed technology and file name as arguments to main. |
| SimpleTestBench | Represents a simple test bench. |
Loads an EDIF design directly into cvt with the capability of writing a JHDL *.java wrapper file.
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