FPGA CAD Tool Directory
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Open source FPGA CAD tool. One of the most widely used FPGA CAD tools around the world. Structurally based, JHDL is a great tool to build a datapath. It is also highly versatile because you can export your design into EDIF format, and then import it into another CAD tool. JHDL can be a stand-alone CAD Tool as well, able to go straight from design in a .java file to simulation & verification to techmapping and writing the design to a .bit file, ready to download to an FPGA part.
JHDL support is also ongoing at Brigham Young University's Configurable Computing Lab. Current discussions go on with it's mailing list.
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Relatively new, this open source EDIF tool suite has already become very powerful. Allowing one to parse EDIF files. After the EDIF is parsed in, the user can then manipulate the datastructure that contains it, and then export the edited EDIF file.
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Extensive Power tools and modeling used for FPGA space research. FPGA systems on earth have no problems, but when they're brought to areas with increased radiation, their reliability goes down as single event upsets begin to occur. This site has some great tools to overcome these problems.
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Ever heard or open source? This site features open IP cores. These can greatly speed up the design process. The cores are like ongoing open source projects, and are constantly updated and fixed, however, IPs are in nature fairly limited. It is very important that you know exactly what the IP core is doing before using it. You wouldn't want to use an IP core, and then only find out months into the project later that it doesn't have all the functionality you thought it had.
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FreeHDL is an open source VHDL simulator project. The project's goals are to have a graphical waveform viewer, source level debugger, VHDL compliancy, commercial quality (not like some open source, free projects out there), and to primarily work with Linux.
This project has quite a few features. Their syntax is a little different, but it's quite similar to Xilinx's version of the simulator, but this one's entirely free and open source, meaning anyone could further extend it and/or add commands for their use.
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With already 25,403 registered users and 17 hosted projects, and counting, SystemC™ is a C++ based CAD Tool. It has hardware primitives that are embedded in C++ class libraries. SystemC™, due to being based on C++, is very fast as a hardware modeling language.
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RHDL an 'Agile HDL', based on an object orientated language like JHDL, except at a higher level due to the typelessness of Ruby, allows the design process to be more high level than conventional object orientated langues. The intent with RHDL is to be able to simulate and verify using testbench designs.
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